In recent years, development is advancing of development of switchable large-current power semiconductor circuit elements. A power conversion apparatus configured from a semiconductor device using the power elements is expected to offer the ability to efficiently supply electric power to a load, such as a motor or else. Accordingly, such apparatus is widely employed for the purpose of motor-driving of movable bodies, such as electric trains or automobiles or like vehicles. In particular, in hybrid cars, an engine and an electric motor are in combined use for enabling creation of increased torque from low rotations of the motor and the storage of a regenerative energy to a battery module. Adding thereto an idle stop system permits achievement of high fuel consumption ratios while reducing production of carbon dioxides (CO2).
Power semiconductor circuit elements for use in power converters are faced with a problem as to the presence of steady energy losses due to current flow and switching losses in switching events. In order to increase the efficiency of the power conversion, development is advancing of a power semiconductor circuit element with reducibility of these two kinds of losses along with a semiconductor device and power converter using the same.
Generally, power semiconductor circuit elements are such that as the withstanding voltage at the time of turn-off becomes higher, the thickness of a circuit element increases due to relaxation of an internal electric field of semiconductor. In view of this, in order to lower the loss, it is important to use a power semiconductor element with its breakdown voltage as low as possible.
However, upon switching of a power converter, the voltage being applied to a power semiconductor circuit element steeply rises up in potential due to a rapid current change thereof and also the presence of parasitic inductance components at electrical interconnect wires. To provide the robustness against such rise-up or “jumping” voltage, the power converter is designed to use a power semiconductor circuit element having its voltage withstandability that is approximately two times greater than the power supply voltage. In addition, in order to suppress the jumping voltage, the development is advancing for a so-called low-inductance semiconductor device with reduced wire parasitic inductance and also a power converter using the same.
One prior known structure is disclosed in Japanese Patent Laid-open No. Hei 11 (1999)-4584, which has a linear array of power semiconductor circuit elements on the same substrate surface while letting a planar multilayered wiring conductor be provided in parallel with the array. Stacking is done to permit electrical currents to flow in the planar wiring conductor so that these are opposite in direction to each other to form a reciprocative current flow path, thereby attempting to realize electrical interconnect wires of low inductance. It is also taught by said Patent Document that the wires of an inverter device are stacked in a way which follows: P line conductors on the positive polarity side are formed in a lowermost layer, output-side U line conductors are in an intermediate layer, and negative polarity-side N line conductors are in an uppermost layer.
Additionally, Japanese Patent Laid-open No. 2001-332688 discloses therein a technique for designing each of the positive P line conductors, output-side U line conductors and negative N line conductors by a “wide” electrode with its width greater than the thickness thereof, with respect to two power semiconductor circuit elements. This Patent Document also discloses an approach to achieving low inductance by stacking or laminating the P-, U- and N-line conductors in an order of P-U-N.
Japanese Patent Laid-open No. 2003-197858 discloses therein a technique for realizing low inductance by stacking, for layout, external connection electrodes of the positive, negative and output sides between more than two positive and negative side power semiconductor circuit elements.